The present invention relates to a solid electrolytic capacitor for use in an electronic apparatus, and a method of fabricating the same.
In general, electrolytic capacitors for use in the secondary side of a power supply circuit, or with the CPU of a personal computer have been desired for decreased dimensions and increased capacitance, as well as minimizing both the equivalent serial resistance (ESR) and the equivalent serial inductance(ESL).
FIG. 10 illustrates the typical structure of a conventional chip solid electrolytic capacitor. More specifically, capacitor element 26 has a positive electrode 20 made of a valve metal in which positive electrode lead 21 is embedded and connected at its proximal end with dielectric oxide film 23, electrolyte layer 24, and negative electrode layer 25 in a sequence. Positive electrode lead 21 of capacitor element 26 is welded to external positive electrode terminal 27, while negative electrode layer 25 is connected by conductive adhesive 28 to external negative electrode terminal 29. Capacitor element 26 and its joints are protected with resin coating 30 shaped by mold forming. External positive electrode terminal 27 and external negative electrode terminal 29, projecting outwardly from opposite ends of resin coating 30, are folded down to extend vertically along the surface of resin coating 30 and then horizontally along the bottom side of resin coating 30, whereby the shape of a chip solid electrolytic capacitor can be determined.
To improve the productivity of such capacitors, a method of modifying a solid of the chip into a wafer form is disclosed in Japanese Patent (Publication No. 8-31696).
Recently, for minimizing ESR, a solid electrolytic capacitor employing, as the solid electrolyte, a functional polymer which is remarkably higher in electric conductivity than a conventional material or manganese dioxide has been proposed.
The above mentioned conventional chip solid electrolytic capacitor however has a considerable size of dead space created by the feed-out region and the folded leads at the joints between positive electrode lead 21 and external positive electrode terminal 27 and between negative electrode lead 25 and external negative electrode terminal 29 in capacitor element 26. Accordingly, the installation of capacitor element 26 will hardly be efficient, hence making the chip capacitor of favorably minimized dimensions much difficult. The feed-out of positive electrode 20 is connected by a point to positive electrode lead 21. This may increase the resistance to the positive electrode output, hence increasing ESR of the conventional chip solid electrolytic capacitor.
Alternatively, a small-sized, large-capacitance chip solid electrolytic capacitor employs traditionally a high capacitance/voltage (CV) powder of valve metal. The high CV powder is increased in the actual surface area by reducing the diameter of each primary particle. This increases the electrostatic capacitance per unit volume, but decreases mass of bubbles in the particles after shaping and sintering. Accordingly, when the electrostatic capacitance is fed out from a solid electrolyte layer after the development of an oxide film, the resistance of the solid electrolyte layer increases and ESR thus increases in theory. Also, as its impregnation of the solid electrolyte solution is relatively low, a capacitance achievement rate, which is expressed by a ratio of the electrostatic capacitance of a liquid electrolyte to the electrostatic capacitance of a solid electrolyte, may possibly be declined.
Moreover, as the positive electrode of such a conventional capacitor is a solid material, its productivity will remain low. Even the high CV powder may fail to demonstrate its advantage in increasing a capacitance and thus hardly minimize ESR.
It is an object of the present invention to provide a solid electrolytic capacitor in which the capacitor element has improved volumetric installation efficiency, hence minimizing the overall thickness and lowering the equivalent serial resistance (ESR).
The solid electrolytic capacitor according to the present invention includes a capacitor element which comprises:
(a) a positive electrode lead made of a valve metal in any form selected from a net, a sheet, a foil, and their modification with rough surface;
(b) a positive electrode body which is fabricated by forming and sintering a desired shape of the valve metal and which is arranged for the positive electrode lead to be embedded with one end exposed to the outside; and
(c) a dielectric oxide film and a negative electrode layer provided on the surface of the positive electrode body.
The solid electrolytic capacitor further comprises a positive electrode terminal connected to the exposed end of the positive electrode lead extending from the capacitor element, a negative electrode terminal connected to the negative electrode layer, and an insulating housing resin covering entirely the capacitor element with the positive electrode terminal and the negative electrode terminal partially exposed to the outside.
The capacitor is consequently decreased in thickness while eliminating redundant of the space created by the feed-out for external connection. As the charge feed-out distance between the positive electrode and the negative electrode is minimized, the equivalent serial resistance pertinent to the chip solid electrolytic capacitor can be lowered.